1. Field of the Invention
The present invention relates to memory cell precharging, and more particularly to precharging blocks of memory in a random access memory.
2. State of the Art
Most memories consist of storage cells which produce differential outputs (referred to as bitline true (T) and complement (C) signals). For either read or write operations, differential voltage levels are developed between the T and C bitlines. In some memories (e.g., static random access memories (RAMs)), the T and C bitlines are initially pre-charged to the same voltage level (often to a logic HIGH voltage level) to prepare for the next access. Once column and row select signals are applied and bitlines are precharged, the bitlines are read such that a differential signal is developed across the once precharged bitlines. In order to perform the next bitline read, the bitlines must first be recharged again. Hence, the amount of time it takes to perform bitline precharging determines part of the memory access cycle time. Specifically, the longer the precharge time, the longer the total memory access cycle time. Consequently it is advantageous to reduce precharge times thereby reducing overall access times.
Large memory arrays are often divided into N blocks of columns of memory cells (FIG. 1A). An input address is decoded and x-decoder select signals and y-decoder select signals are applied to the memory array such that a single block of columns is accessed and sensed by a set of sense amplifiers. The data sensed by the amplifiers is then provided to M output ports. Each of the N blocks of columns is further divided into M (i.e., the number of output ports) sub-blocks of columns having m columns each (FIG. 1B). For instance, a 1M bit (i.e., 1.times.10.sup.6 bit) memory arranged in a 1K bits.times.1K bits array configuration (i.e., 1024 rows and 1024 columns) might be divided into eight blocks (i.e., N=8) of 128 columns each. And, in the case when the 1M bit memory has four outputs (i.e., M=4), each 128 column block is divided into four sub-blocks having 32 columns (i.e., m=32) each.
Each sub-block of columns has a corresponding sense amplifier 10 (FIG. 1B). Hence, for an M output port memory system, each block of columns has M corresponding sense amplifiers. When a given block is accessed by decoded x and y select signals, each sub-block provides one differential signal out of m differential signals from its m columns to its corresponding sensor amplifier. For instance, in the case in which a block of columns divided into 32 column sub-blocks (m=32) is accessed, each sub-block outputs 1 differential signal out of 32 possible signals to its corresponding sense amplifier.
As shown in FIGS. 1A and 1B, the input address is decoded to provide x select signals and y select signals which select the M cells in the array to provide data to the M output ports. In the case of a memory structure such as shown in FIG. 1A, the x and y select signals select one of the N blocks and one column in each sub-block. Column selection is performed using pass or select gate pairs 20-22 (FIG. 1C) coupled in series with each bitline pair (bit and bit/) and having their gates coupled to differential y-select signals y0 and y0/ through ym and ym/.
When a pass gate pair is selected, (e.g., y0=1, y0/=0), an electrical path is established from the cell to one of the M sense amplifiers and depending on the x-select signals, data is sensed from a selected cell. The differential y-select signal y0 and y0/ through ym and ym/ are coupled to the sub-blocks 1-M such that nonadjacent bitline pairs provide the data to the output ports. For instance, in the case in which the differential y-select signal y1=1 and y1/=0, then bitline pair 21 in each sub-block provides data from non-adjacent bitline pairs to a set of M sense amplifiers.
Since each sub-block provides one output signal, it is common practice to precharge all bitlines, in all of the sub-blocks in a given selected block of columns. For instance, all of the columns of block N are charged to prepare for accessing M columns from the block of columns. In the case of a block having 128 columns, all 128 bitline pairs (i.e., true and complement) are charged. Charging circuitry is generally implemented with two PMOS devices 30 and an equalizing device 31 have their gates coupled to a precharge signal 32 (FIG. 1D). When the precharge signal is driven low, devices 30 and 31 are turned on and pull bitline and bitline/ to the pre-charge voltage (Vpc), (note, device 31 equalizes bitline and bitline/). Precharge signal 32 enables devices 30 and 31 in a single block of columns to precharge the block in preparation of accessing it. The precharge signal is either synchronously or asynchronously applied after the read operation has been completed.
The problem with this type of access and precharge memory system technique is that as the number of columns per block increases, the capacitive loading associated with each column for charging the columns also increases. As a result, it takes longer to properly charge all bitlines in a given block thereby resulting in an overall increase in access time due to longer precharge times.
The present invention is a manner in which to minimize the impact of precharging in a memory system by restructuring memory array column accessing and performing precharging on smaller numbers of columns during the access cycle.